1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly to a semiconductor memory device such as a dynamic RAM comprising an active pull-up circuit.
2. Description of the Prior Art
In a dynamic MOS RAM, an active pull-up circuit operates after sense amplification of a bit line potential according to data stored in memory cells, whereby the bit line potential on the side of a high level is pulled up to a voltage equal to or higher than a power supply voltage Vcc.
FIG. 1 is a circuit diagram showing a bit line sense system in a conventional dynamic RAM. Referring to FIG. 1, a pair of bit lines BL and BL are connected to data buses I/O and I/ through transistors Q.sub.00 and Q.sub.01, respectively. On-off control of those transistors Q.sub.00 and Q.sub.01 is made by an output of a column decoder 1. Memory cells MC of a 1-transistor 1-capacitor type are connected to each pair of bit lines in an alternate manner. FIG. 1 shows only one memory cell MC for the purpose of simplification of the illustration. Each memory cell MC is connected with a word line WL. Connection or disconnection of the memory cells MC with or from the bit lines BL and BL is controlled by selection of the word lines WL. A dummy memory cell DMC is connected to each of the bit lines BL and BL. FIG. 1 shows only one dummy memory cell DMC connected to the bit line BL. Those dummy memory cells DMC are connected with dummy word lines WLDM. Connection or disconnection of the dummy memory cells with or from the bit lines BL and BL is controlled by selection of the dummy word lines WLDM. A precharge voltage supply V.sub.PR is connected to the bit lines BL and BL through transistors Q.sub.PR0 an Q.sub.PR1, respectively. On-off control of the transistors Q.sub.PR0 and Q.sub.PR1 is made by a clock signal .phi..sub.PR.
In addition, a sense amplifier SAo and an active pull-up circuit APo are connected to each pair of bit lines BL and BL. The sense amplifier SAo serves to detect a potential of the bit lines after selection of a memory cell to bring the potential of the bit line of the low level to a ground level. Operation of the sense amplifier SAo is controlled by a clock signal .phi..sub.S. The active pull-up circuit APo comprises transistors Q.sub.AP0, Q.sub.R0 and a capacitor C.sub.R0 associated with the bit line BL, as well as transistors Q.sub.AP1, Q.sub.R1 and a capacitor C.sub.R1 associated with the bit line BL. The transistor Q.sub.AP0, which is provided between the bit line BL and a power supply Vcc, serves to pull up the bit line BL. The capacitor C.sub.R0 serves to increase a gate potential of the transistor Q.sub.APO. An end of the capacitor C.sub.R0 is connected to a gate of the transistor Q.sub.AP0 and the other end thereof receives a clock signal .phi..sub.R. The transistor Q.sub.R0 serves to precharge the capacitor C.sub.R0 with a precharge voltage of the bit line BL and this transistor Q.sub.R0 is provided between the bit line BL and the above stated one end of the capacitor C.sub.R0. The respective gates of these transistors Q.sub.R0 and Q.sub.R1 receive the clock signal .phi..sub.P. The transistors Q.sub.R1, Q.sub.AP1 and the capacitor C.sub.R1 as the circuit elements associated with the bit line BL are arranged symmetrically with respect to the transistors Q.sub.R0, Q.sub.AP0 and the capacitor C.sub.R0 as the circuit elements associated with the bit line BL.
In reality, a semiconductor memory comprises a plurality of pairs of bit lines BL and BL and memory cells MC associated with those pairs of bit lines BL and BL are arranged in a matrix.
FIG. 2 is a timing chart showing operation timing of the circuit shown in FIG. 1. Referring to FIG. 2, .phi..sub.S, .phi..sub.R, .phi..sub.P and .phi..sub.PR correspond to the respective clock signals shown in FIG. 1; BL and BL represent change in the potential of the bit lines BL and BL; and WL represents change in the potential of the word line WL. RAS represents a row address strobe signal. The row address strobe signal RAS is a signal for defining a non-active period and an active period. In addition, Icc represents change in current flowing from the power supply to the semiconductor memory device shown in FIG. 1. In the following, operation of the circuit in FIG. 1 will be dscribed with reference to FIG. 2.
First, the row address strobe signal RAS falls to start the active period. In this active period, a row address signal (not shown) is latched and the latched row address signal is supplied to a row address decoder (not shown). The row address decoder decodes the row address signal supplied thereto and provides an output. In response to this output, any one of the word lines WL and any one of the dummy word lines WLDM connected to the row address decoder are selected and rise to a high level. As a result, a potential difference is caused in the pair of bit lines BL and BL according to the information stored in the memory cell MC and the dummy memory cell DMC associated with the selected lines. After that, the clock signal .phi..sub.S rises to enable the sense amplifier SAo so that the bit line of the low potential is brought to the ground potential. Then, the clock signal .phi..sub.R rises to start active pull-up operation. In this active pull-up operation, the bit line of the high level is pulled up from the precharge voltage V.sub.PR to the power supply voltage Vcc, oppositely to sense amplifying operation. For example, let us assume that the bit line of the high level is BL out of the pair of bit lines BL and BL. Since a node N1 of the gate of the transistor Q.sub.AP0 and the capacitor C.sub.R0 is maintained in advance at the precharge voltage V.sub.PR of the bit line BL by turning on of the transistor Q.sub.R0, the node N1 rises to a voltage higher than the power supply voltage Vcc by boost effect of the capacitor C.sub.R0 when the clock signal .phi..sub.R rises. As a result, the transistor Q.sub.AP0 is conducted to a high degree and the bit line BL is pulled up to the power supply voltage Vcc. On the other hand, as for the bit line BL of the low level, the potential at a node N2 of the gate of the transistor Q.sub.AP1 and the capacitor C.sub.R1 is equal to the ground level and consequently if the clock signal .phi..sub.R rises, the potential at the node N2 does not rise and the transistor Q.sub.AP1 does not turn on. Thus, the active pull-up circuit APo pulls up only the bit line of the high level to the power supply voltage Vcc.
When the above stated active pull-up operation is performed, half of the total number of bit lines are changed from the precharge voltage V.sub.PR to the power supply voltage Vcc and as a result consumption of electric current Icc from the power supply presents an acute peak as shown in FIG. 2. In addition, when the active period comes to an end after the rise of the row address strobe signal RAS, the selected word line WL and dummy word line WLDM fall so that all of the bit lines are precharged with V.sub.PR. At this time also, consumption of electric current Icc from the power supply presents an acute peak as shown in FIG. 2.
The peak values of the electric current Icc at the time of active pull-up operation and at the time of precharging bit lines are considerably large. Accordingly, requirements for a power supply capacity of a memory system become severe.
A conventional method for decreasing such peak current at the time of precharging bit lines is indicated for example in "A 60 ns 256K.times.1 Bit DRAM Using LD.sup.3 Technology and Double-Level Metal Interconnection", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, pp. 585 October, 1984, in which a memory cell array, namely, a semiconductor memory device is divided into a plurality of blocks and precharging operation for bit lines is started sequentially with a time lag for each block.
However, according to such a conventional method as disclosed in the above stated document, a peak current at the time of precharging bit lines can be decreased but a peak current at the time of active pull-up operation can not be reduced.
If an active cycle is terminated before the completion of active pull-up operation, the high level stored in the memory cell is lowered, causing a large influence in effective margin for operation of the memory. For this reason, in such a method as in the above stated document in which precharging operation for bit lines is started with a time lag for each block, it is necessary to assure a sufficiently long period for active pull-up operation from the start of pull-up operation in each block (performed simultaneously for each block) till the start of a non-active period of the block where precharging operation for bit lines is started first. However, in such case, a period of time from the start of active pull-up operation to the start of precharging operation for bit lines becomes unnecessarily long in blocks where precharging operation for bit lines is started late, and a memory cycle period as a whole is made unfavorably long.